1. Field of the Invention
The present invention relates generally to very-large-scale-integrated (VLSI) metal interconnection structures, electrical conductors, thin-film conductive stripes and fabrication methods therefor, and more particularly, to providing improved copper alloy conductors for such structures
2. Description of the Prior Art
In the past, VLSI fabrication steps utilized aluminum as the single metallurgy for contacts and interconnects in semiconductor regions or devices located on a single substrate. Aluminum was desirable because of its low cost, good ohmic contact and high conductivity. However, pure aluminum thin-film conductive stripes had undesirable qualities, such as, a low melting point which limited its use to low temperature processing, diffusion into the silicon during annealing which leads to contact and junction failure, and electromigration. Consequently, a number of aluminum alloys were developed which provided advantages over pure aluminum. For example, in U.S. Pat. No. 4,566,177, a conductive layer of an alloy of aluminum containing up to 3% by weight in total of silicon, copper, nickel, chromium and/or manganese was developed to improve electromigration resistance. In U.S. Pat. No. 3,631,304 aluminum was alloyed with aluminum oxide to improve electromigration resistance.
Emerging VLSI technology has placed stringent demands on Back-End-of-the-Line (BEOL) wiring requirements arising from high circuit densities and faster operating speeds required of future VLSI devices. This will require higher current densities in increasingly smaller conduction lines. Thus, higher conductance wiring is required which would require either larger wiring cross-sections for aluminum alloy conductors or a higher conductance wiring material. The trend in the industry has been to develop the latter using pure copper because its conductivity is higher than the conductivity of aluminum.
In the formation of VLSI interconnection structures, copper is deposited into a line, via or other recess to interconnect semiconductor regions or devices located on the same substrate. Copper is known as a cause of problems at semiconductor device junctions and hence, any diffusion of copper into the silicon substrate can cause device failure. In addition, pure copper does not adhere well to oxygen containing dielectrics such as silicon dioxide and polyimide. Thus, current practice for BEOL copper metallization includes 1000 Angstroms or thicker of a diffusion barrier and/or adhesion layer. For example, FIG. 1 is a schematic drawing of a portion of a VLSI interconnection structure 10. In structure 10, copper plug 12 is used to interconnect conductive layers and semiconductor devices located in a VLSI device. Recess 14 is defined in dielectric layer 16 disposed on the surface of the copper conduction line 18. Physical vapor deposition or chemical vapor deposition methods are used to fill interconnection structure 10 with adhesion layer 20 and copper plug 12. Since copper does not adhere well to oxygen containing dielectrics nor to itself, layer 20 is used as an adhesive to allow the copper plug 12 to adhere to dielectric layer 16 and copper conduction line 18. The adhesion layer 20 is composed of a refractory metal composite such as titanium-tungsten (TiW) or titanium-nitride (TiN).
FIG. 2 is a schematic diagram of a portion of another VLSI interconnection structure 22. The copper plug 12 in interconnection structure 22 is used to contact semiconductor region 24 formed in silicon substrate 26. Illustratively, region 24 is a metal silicide contact composed of tantalum silicide (TaSi.sub.2) or cobalt silicide (CoSi.sub.2). Since copper reacts easily with silicides at low temperatures thereby diffusing into silicon substrate 26, diffusion and adhesion layer 20 is used to prevent such diffusion and to allow copper plug 12 to adhere to dielectric layer 16.
There are several problems with using a diffusion barrier and/or adhesion layer, such as layer 20, for BEOL copper metallization. In structure 10, by encasing a portion of the recess 14, the adhesion layer 20 interposes a layer between the copper conductor 12 and the copper conduction line 18. This gives rise to contact resistances and the added series resistance of the adhesion layer 20. In structures 10 and 22, although the diffusion barrier and/or adhesion layer 20 is conductive, it is more resistive than pure copper and its presence decreases the available copper cross-sectional area of recess 14, thereby diminishing the current-carrying capacity of micron or smaller lines. Thus, in order to meet the current demands on BEOL wiring requirements, there is a need to develop copper metallization which does not have the above problems.